[SatNews] Aitech Defense Systems Inc. has announced that their SP0 3U CompactPCI SBC has passed final 100 kRad (Si) testing
The data collected during testing helped determine SEE sensitivity. Based on this information, Aitech calculated that the SP0 will be subject to only one single event functional upset per 1,186 days (3 years and 91 days) during orbit. This takes into account the South Atlantic Anomaly (SAA) with the SP0's L1 and L2 caches enabled. Any performance degradation due to SEE mitigation was below the measurement error floor.
The testing has validated the SP0's reliable operation across a wide range of orbits. LEO covers 160 km (100 miles) to 2,000 km (1,250 miles); MEO is from 2,000 km (1,250 miles) to approximately 35,000 km (22,000 miles); and GEO is 36,000 km (22,236 miles) and above. The compact 3U SBC provides exceptional on-board functionality combined with a low power consumption of only 10 W. Using a MPC8548E PowerQUICC-III processor enables a processing speed of 1.17 GHz as well as 333.3 MHz of core complex bus (CCB) and fast DDR1 memory speeds.
The SP0's processor includes an e500 System-on-Chip (SoC) integrating both an L1 cache with 32 KB instruction and 32 KB data and a 512 KB L2 cache. A large user Flash of 1 GB is standard, with the option to expand up to 8 GB. The large on-board memory also includes up to 512 MB of fast DDR1 SDRAM with ECC protection for high data integrity as well as 512 KB of redundant Boot Flash to meet both processor and application needs. The SP0 includes extensive I/O, including two Gigabit Ethernet ports, four asynchronous, high-speed serial communications ports and up to five general purpose discrete I/O channels, all of which are routed to the rear panel connectors. This reduces the number of additional peripheral cards needed for a fully functional subsystem.
For additional on-board functionality and performance, the SP0 includes an industry-standard PMC slot as well as from four to eight PCI Express lanes or four Serial RapidIO lanes and dual PCI buses. Three watchdog timers offer exceptional system safety parameters and reliability. One watch dog timer, located within the SoC processor, generates an internal CPU interrupt to alert the application of a pending fault. After the first timer expires and then the second timer expires, a non-maskable hardware reset is performed, which also resets the entire board. Located in the on-board FPGA, the third timer can reset the whole board or only certain I/O devices after the expiration period.
- Tested to 100 kRad (Si) TID; no latch up
- PowerPC MPC8548E PowerQUICC-III processor
- e500 SoC with 32 KB instruction/32 KB data L1 cache and 512 KB L2 cache
- Low power: 10 W consumption